Discretized DLGN on FPGA (Terasic DE0 / Cyclone-III)

Converted a trained differentiable-logic classifier (MONK) to synthesizable Verilog and deployed on a Terasic DE0 (Cyclone-III).

• Throughput: ~2.38M samples/s
• Latency: ~420 ns
• Power: ~155 mW

Focus areas: quantization/discretization, RTL partitioning, timing closure, and power measurement.

Links: Add repository / write-up / video when ready.