A few highlights that connect ML with embedded/FPGA work.
Discretized DLGN on FPGA (Terasic DE0 / Cyclone-III)
2.38M samples/s throughput, ~420ns latency, ~155mW. Verilog from trained logic model.
Projects
IjtihadAI — Arabic RAG Chatbot Toolkit
Scraper → embeddings → vector DB → Gradio UI (LangChain).
LogicTreeUNet — Differentiable-Logic Upsampling for Segmentation
Extended Conv-DLGN to a U-Net with logic upsampling; IoU 0.956 (MNIST), 0.8135 (CamVid-road).